Akademik Veri Yönetim Sistemi
Journal of Micromechanics and Microengineering, cilt.36, sa.4, 2026 (SCI-Expanded, Scopus)
The heterogeneous integration of functional substrates with vacuum-sealed microcavities remains a significant challenge in the fabrication of robust microelectromechanical systems (MEMS). Conventional fusion bonding requires elevated thermal budgets, which can compromise the integrity of temperature-sensitive device architectures. To overcome these limitations, this paper presents, to the best of our knowledge, for the first time, an atomic layer deposition alumina (Al2O3) enabled wafer-level anodic bonding process for the integration of low-temperature co-fired ceramic (LTCC) and silicon-on-insulator (SOI) substrates. The bonding mechanism was first optimized at the chip level, where current–time analysis across 150 nm, 250 nm, and 300 nm interlayer thicknesses revealed that the bonding current is inversely proportional to the interlayer thickness. This optimized process was successfully scaled to wafer-level bonding using functional LTCC wafers (with electrical through vias and patterned cavities) and SOI wafers. In this architecture, the 150 nm Al2O3 layer was selected as the optimal trade-off for balancing dielectric insulation and ionic conductivity. This interlayer plays a pivotal dual role, facilitating efficient ion migration for rapid bonding while exhibiting high dielectric breakdown. The bonding integrity and structural stability of the 12 µm-thick suspended membranes over the MEMS cavities were comprehensively characterized using bonding current monitoring, scanning acoustic microscopy (SAM), and 3D surface profilometry. Quantitative yield analysis further demonstrated the high mechanical reliability of the integrated devices after dicing. This work establishes a high-performance, low-temperature alternative to conventional fusion-bonded cavity silicon-on-insulator (Cavity-SOI) architectures, offering a scalable pathway for next-generation integrated MEMS sensors.